Dither is intentionally added noise commonly used to mask non-linear behavior or non-ideal behavior in a circuit system. The process of generating dither noise is referred to as “dithering.”
Quantization during analog to digital conversion may cause nonlinearities or non-idealities in output signals. In analog-to-digital converters (ADC), dithering may be used to de-correlate successive non-linear quantization errors. In other words, dither may be used to mask or smooth out nonlinearities such as abrupt or sharp changes in ADC transfer functions. The theory behind dithering is well known in the field of mixed signal processing.
FIG. 1 illustrates a conventional differential amplifier (100) commonly known in the art as the “long-tailed pair.” This differential amplifier has a pair of transistors (102, 104) such as NMOS transistors commonly connected at the source ends, each of which may be coupled to a voltage reference VDD via a resistor load R (106, 108) at the drains of the transistors. The amplifier (100) may also include a common current source (110) that provides a bias current Ibias through the transistors (102, 104). The bias current may set the operating point for the transistors. The amount of current passing through loads (106, 108) may be controlled by the respective input voltage signals Vin+ and Vin− at the inputs of the transistors. Output voltages may be established at output terminals Vout+ and Vout− based on the output currents.
It is commonly known that a differential amplifier amplifies the difference between the two input voltages (Vin+−Vin−) by a constant factor (called differential gain) to generate an output signal (Vout+−Vout−). Conventionally, the Ibias in the long-tailed pair supplies approximately constant current to the amplifier to set operating points of the transistors (102, 104). For such a conventional analog differential amplifier, the output difference (Vout+−Vout−) may be at a fixed ratio of the input voltage difference (Vin+−Vin−).
U.S. Pat. No. 6,172,629 to Fetterman (the '629 patent) describes methods and systems that use randomized voltage levels to dither a pipelined ADC. For example, FIG. 4 of the '629 patent shows a differential amplifier that includes a number of composite transistor pairs (T1A/T2A, T1B/T2B, T1C/T2C, and T1D/T2D). The opening and closing of T1B/T2B, T1C/T2C, and T1D/T2D are controlled by input voltage signals at gate pairs of M11/M21, M12/M22, and M13/M23, whose values may be determined by a random number generator. Through the randomized opening and closing of M11/M21, M12/M22, and M13/M23, the effective size of T1A/T2A pair may be changed randomly. Even though the effective size of T1A/T2A changes, the current source (110) was kept constant. To achieve the dithering objective, the '629 patent used multiple input transistors that may be switched on and off. However, when the input transistors are switched on and off, the inputs and outputs of the amplifier may be loaded with parasitics, which may cause undesirable effects. Additionally, for operations at low supply voltages, the configuration as shown in FIG. 4 of the '629 patent may have limited headroom. Under low supply voltages, the adequate voltage drop across the drain/source of a composite T may become an important design parameter to keep T in the saturation (i.e., high gain) region of operation. Voltage may drop across the inserted switch M between input transistor T and load resistor R and leave less voltage headroom for the input transistor T.
Therefore, there is a need for a dithering apparatus or method that has less parasitic effects and has greater headroom than previous attempts.